Searched refs:registerName (Results 1 - 5 of 5) sorted by relevance
| /gem5/src/arch/riscv/insts/ |
| H A D | mem.cc | 51 ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " <<
52 offset << '(' << registerName(_srcRegIdx[0]) << ')';
60 ss << mnemonic << ' ' << registerName(_srcRegIdx[1]) << ", " <<
61 offset << '(' << registerName(_srcRegIdx[0]) << ')';
|
| H A D | amo.cc | 66 ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", ("
67 << registerName(_srcRegIdx[0]) << ')';
75 ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", ("
76 << registerName(_srcRegIdx[0]) << ')';
85 ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", "
86 << registerName(_srcRegIdx[1]) << ", ("
87 << registerName(_srcRegIdx[0]) << ')';
95 ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", "
96 << registerName(_srcRegIdx[1]) << ", ("
97 << registerName(_srcRegId
[all...] |
| H A D | standard.cc | 50 ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " <<
51 registerName(_srcRegIdx[0]) << ", " <<
52 registerName(_srcRegIdx[1]);
60 ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", ";
62 ss << registerName(_srcRegIdx[0]) << ", ";
|
| H A D | compressed.cc | 47 ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " <<
48 registerName(_srcRegIdx[0]);
|
| /gem5/src/arch/riscv/ |
| H A D | utility.hh | 137 registerName(RegId reg) function in namespace:RiscvISA
|
Completed in 6 milliseconds