Searched refs:reg_class (Results 1 - 2 of 2) sorted by relevance

/gem5/src/cpu/
H A Dreg_class.hh93 RegId(RegClass reg_class, RegIndex reg_idx) argument
94 : RegId(reg_class, reg_idx, ILLEGAL_ELEM_INDEX) {}
96 explicit RegId(RegClass reg_class, RegIndex reg_idx, ElemIndex elem_idx) argument
97 : regClass(reg_class), regIdx(reg_idx), elemIdx(elem_idx),
/gem5/src/arch/
H A Disa_parser.py529 reg_class = 'IntRegClass' variable in class:IntRegOperand
542 c_src = src_reg_constructor % (self.reg_class, self.reg_spec)
548 c_dest = dst_reg_constructor % (self.reg_class, self.reg_spec)
601 reg_class = 'FloatRegClass' variable in class:FloatRegOperand
614 c_src = src_reg_constructor % (self.reg_class, self.reg_spec)
617 c_dest = dst_reg_constructor % (self.reg_class, self.reg_spec)
664 reg_class = 'VecRegClass' variable in class:VecRegOperand
705 c_src = src_reg_constructor % (self.reg_class, self.reg_spec)
708 c_dest = dst_reg_constructor % (self.reg_class, self.reg_spec)
812 reg_class variable in class:VecElemOperand
866 reg_class = 'VecPredRegClass' variable in class:VecPredRegOperand
948 reg_class = 'CCRegClass' variable in class:CCRegOperand
1020 reg_class = 'MiscRegClass' variable in class:ControlRegOperand
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