Searched refs:port_name (Results 1 - 11 of 11) sorted by relevance
/gem5/ext/dsent/model/timing_graph/ |
H A D | ElectricalTimingOptimizer.cc | 65 const String& port_name = it->first; local 67 StdCell* inv0 = getTechModel()->getStdCellLib()->createStdCell("INV", port_name + "Driver0"); 69 StdCell* inv1 = getTechModel()->getStdCellLib()->createStdCell("INV", port_name + "Driver1"); 75 createInputPort(port_name, port_info->getNetIndex()); 76 createNet(port_name + "Driver0In"); 77 createNet(port_name + "Driver0Out"); 78 createNet(port_name + "Driver1Out"); 79 assignVirtualFanin(port_name + "Driver0In", port_name); 80 portConnect(inv0, "A", port_name 88 portConnect(getModel(), port_name, port_name + "In"); local [all...] |
/gem5/src/systemc/ext/tlm_core/1/req_rsp/ports/ |
H A D | nonblocking_port.hh | 36 tlm_nonblocking_get_port(const char *port_name) : argument 37 sc_core::sc_port<tlm_nonblocking_get_if<T>, 1>(port_name) 55 tlm_nonblocking_peek_port(const char *port_name) : argument 56 sc_core::sc_port<tlm_nonblocking_peek_if<T>, 1>(port_name) 74 tlm_nonblocking_put_port(const char *port_name) : argument 75 sc_core::sc_port<tlm_nonblocking_put_if<T>, 1>(port_name)
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/gem5/ext/systemc/src/tlm_core/tlm_1/tlm_req_rsp/tlm_ports/ |
H A D | tlm_nonblocking_port.h | 35 tlm_nonblocking_get_port( const char *port_name ) : 36 sc_core::sc_port< tlm_nonblocking_get_if< T > , 1 >( port_name ) {} 55 tlm_nonblocking_peek_port( const char *port_name ) : 56 sc_core::sc_port< tlm_nonblocking_peek_if< T > , 1 >( port_name ) {} 76 tlm_nonblocking_put_port( const char *port_name ) : 77 sc_core::sc_port< tlm_nonblocking_put_if< T > , 1 >( port_name ) {}
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/gem5/configs/example/ |
H A D | read_config.py | 139 def __init__(self, object_name, port_name, index): 141 self.port_name = port_name 147 object_name, port_name, whole_index, index = m.groups() 153 return PortConnection(object_name, port_name, index) 156 return '%s.%s[%d]' % (self.object_name, self.port_name, self.index) 159 return cmp((self.object_name, self.port_name, self.index), 160 (right.object_name, right.port_name, right.index)) 289 for port_name, port in obj.__class__._ports.items(): 291 peers = self.config.get_port_peers(object_name, port_name) [all...] |
/gem5/src/python/m5/util/ |
H A D | dot_writer.py | 97 for port_name in simNode._ports.keys(): 98 port = simNode._port_refs.get(port_name, None) 100 full_port_name = full_path + "_" + port_name 101 port_node = dot_create_node(simNode, full_port_name, port_name) 112 for port_name in simNode._ports.keys(): 113 port = simNode._port_refs.get(port_name, None) 116 full_port_name = full_path + "_" + port_name 117 port_node = dot_create_node(simNode, full_port_name, port_name) 307 for port_name in simNode._ports.keys(): 308 port = simNode._port_refs.get(port_name, Non [all...] |
/gem5/src/sim/ |
H A D | cxx_config_ini.cc | 71 const std::string &port_name, 74 return getParamVector(object_name, port_name, peers); 70 getPortPeers(const std::string &object_name, const std::string &port_name, std::vector<std::string> &peers) const argument
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H A D | cxx_config_ini.hh | 72 const std::string &port_name,
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H A D | cxx_config.hh | 207 const std::string &port_name,
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/gem5/ext/dsent/model/ |
H A D | EventInfo.cc | 40 const String& port_name = it->first; local 41 m_trans_info_map_->set(port_name, TransitionInfo());
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H A D | ElectricalModel.cc | 874 const String& port_name = it->first; local 876 const TransitionInfo& trans_info = event_info->getTransitionInfo(port_name);
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/gem5/src/python/m5/ |
H A D | SimObject.py | 1506 for port_name in port_names: 1507 port = self._port_refs.get(port_name) 1531 for port_name in sorted(self._ports.keys()): 1532 port = self._port_refs.get(port_name, None) 1534 print('%s=%s' % (port_name, port.ini_str()), file=ini_file) 1564 for port_name in sorted(self._ports.keys()): 1565 port = self._port_refs.get(port_name, None) 1569 d[port_name] = port.get_config_as_dict() 1607 for port_name in port_names: 1608 port = self._port_refs.get(port_name, Non [all...] |
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