Searched refs:one (Results 1 - 18 of 18) sorted by relevance

/gem5/src/cpu/
H A Dthread_context.cc59 ThreadContext::compare(ThreadContext *one, ThreadContext *two) argument
65 RegVal t1 = one->readIntReg(i);
68 panic("Int reg idx %d doesn't match, one: %#x, two: %#x",
74 RegVal t1 = one->readFloatReg(i);
77 panic("Float reg idx %d doesn't match, one: %#x, two: %#x",
84 const TheISA::VecRegContainer& t1 = one->readVecReg(rid);
87 panic("Vec reg idx %d doesn't match, one: %#x, two: %#x",
94 const TheISA::VecPredRegContainer& t1 = one->readVecPredReg(rid);
97 panic("Pred reg idx %d doesn't match, one: %#x, two: %#x",
102 RegVal t1 = one
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H A Dthread_context.hh313 static void compare(ThreadContext *one, ThreadContext *two);
/gem5/src/systemc/tests/systemc/misc/sim_tests/manual_clock/
H A Dmanual_clock.cpp3 Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
155 sc_signal<bool> zero("zero"), one("one");
159 proc3 p3( "p3", p, q, zero, one );
/gem5/ext/systemc/src/sysc/datatypes/int/
H A Dsc_nbfriends.inc3 Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
27 sc_nbexterns.cpp perform their work on one of their
H A Dsc_signed_bitref.inc3 Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
H A Dsc_unsigned_bitref.inc3 Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
H A Dsc_signed_subref.inc3 Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
H A Dsc_unsigned_subref.inc3 Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
H A Dsc_nbcommon.inc3 Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
28 to ensure only one version of each function, regardless
2743 // Deletions will start from the left end and move one position
2759 // Deletions will start from the left end and move one position
2891 // Deletions will start from the left end and move one position
2907 // Deletions will start from the left end and move one position
/gem5/src/systemc/dt/int/
H A Dsc_nbfriends.inc3 Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
27 sc_nbexterns.cpp perform their work on one of their
H A Dsc_nbcommon.inc3 Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
28 to ensure only one version of each function, regardless
2390 // Deletions will start from the left end and move one position
2406 // Deletions will start from the left end and move one position
2529 // Deletions will start from the left end and move one position
2545 // Deletions will start from the left end and move one position
H A Dsc_signed_bitref.inc3 Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
H A Dsc_unsigned_bitref.inc3 Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
H A Dsc_signed_subref.inc3 Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
H A Dsc_unsigned_subref.inc3 Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
/gem5/src/dev/ps2/
H A Dtypes.hh112 Bitfield<3> one; member in namespace:Ps2
/gem5/ext/systemc/src/sysc/qt/
H A Dmeas.c118 "Performs 1 QT_SP and one QT_ARGS per iteration.",
307 static char const test06_msg[] = "*QT_ARGS(...), QT_BLOCKI one thread";
378 "There is no scheduling performed. Each thread but one is a loop",
389 Each iteration corresponds to one block operation.
392 run `test07_aux2'. Each one of those blocks saving it's sp to
557 test09_user2 (int one, int two) argument
559 assert (one == 1);
562 assert (one == 1);
568 test09_user10 (int one, int two, int three, int four, int five, argument
571 assert (one
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/gem5/src/python/m5/
H A Dparams.py107 # object of this type. Typically generates one or more #include
970 raise TypeError("expected an ethernet address and didn't get one")
1793 # only one copy of a particular node
2088 def is_compat(cls, one, two):
2089 for port in one, two:
2092 return one.role in Port._compat_dict[two.role]

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