Searched refs:numregs (Results 1 - 9 of 9) sorted by relevance

/gem5/util/statetrace/arch/i686/
H A Dtracechild.hh58 numregs enumerator in enum:I686TraceChild::RegNum
64 bool regDiffSinceUpdate[numregs];
H A Dtracechild.cc44 assert(num < numregs && num >= 0);
78 for (unsigned int x = 0; x < numregs; x++) {
85 for (unsigned int x = 0; x < numregs; x++)
/gem5/src/arch/arm/insts/
H A Dsve_macromem.hh58 uint8_t numregs; member in class:ArmISA::SveLdStructSS
65 dest(_dest), gp(_gp), base(_base), offset(_offset), numregs(_numregs)
67 numMicroops = numregs * 2;
71 for (int i = 0; i < numregs; ++i) {
76 for (int i = 0; i < numregs; ++i) {
77 microOps[i + numregs] = new MicroopDeIntrlvType<Element>(
103 for (int i = 0; i < numregs; ++i) {
105 if (i < numregs - 1)
129 uint8_t numregs; member in class:ArmISA::SveStStructSS
136 dest(_dest), gp(_gp), base(_base), offset(_offset), numregs(_numreg
202 uint8_t numregs; member in class:ArmISA::SveLdStructSI
274 uint8_t numregs; member in class:ArmISA::SveStStructSI
[all...]
/gem5/util/statetrace/arch/arm/
H A Dtracechild.hh73 numregs enumerator in enum:ARMTraceChild::RegNum
91 bool regDiffSinceUpdate[numregs];
H A Dtracechild.cc64 for (int x = 0; x < numregs; x++) {
75 uint64_t message[numregs + 1];
78 for (int x = 0; x < numregs; x++) {
112 assert(num >= F0 && num < numregs);
137 for (unsigned int x = 0; x < numregs; x++)
/gem5/util/statetrace/arch/sparc/
H A Dtracechild.hh67 numregs enumerator in enum:SparcTraceChild::RegNum
78 bool regDiffSinceUpdate[numregs];
H A Dtracechild.cc78 assert(num < SparcTraceChild::numregs && num >= 0);
195 for (unsigned int x = 0; x < numregs; x++)
202 for (unsigned int x = 0; x < numregs; x++)
/gem5/util/statetrace/arch/amd64/
H A Dtracechild.hh88 numregs enumerator in enum:AMD64TraceChild::RegNum
97 bool regDiffSinceUpdate[numregs];
H A Dtracechild.cc85 assert(num < numregs && num >= 0);
221 for (unsigned int x = 0; x < numregs; x++)
228 for (unsigned int x = 0; x < numregs; x++)

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