Searched refs:msi (Results 1 - 2 of 2) sorted by relevance
| /gem5/src/arch/riscv/ | ||
| H A D | interrupts.hh | 80 mask.mei = mask.mti = mask.msi = 1; |
| H A D | registers.hh | 644 Bitfield<3> msi; member in namespace:RiscvISA |
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