Searched refs:miscRegFile (Results 1 - 4 of 4) sorted by relevance

/gem5/src/arch/riscv/
H A Disa.cc50 miscRegFile.resize(NumMiscRegs);
62 std::fill(miscRegFile.begin(), miscRegFile.end(), 0);
64 miscRegFile[MISCREG_PRV] = PRV_M;
65 miscRegFile[MISCREG_ISA] = (2ULL << MXL_OFFSET) | 0x14112D;
66 miscRegFile[MISCREG_VENDORID] = 0;
67 miscRegFile[MISCREG_ARCHID] = 0;
68 miscRegFile[MISCREG_IMPID] = 0;
69 miscRegFile[MISCREG_STATUS] = (2ULL << UXL_OFFSET) | (2ULL << SXL_OFFSET) |
71 miscRegFile[MISCREG_MCOUNTERE
[all...]
H A Disa.hh68 std::vector<RegVal> miscRegFile; member in class:RiscvISA::ISA
/gem5/src/arch/mips/
H A Disa.cc95 miscRegFile.resize(NumMiscRegs);
99 miscRegFile[i].resize(1);
122 miscRegFile[per_vpe_regs[i]].resize(numVpes);
138 miscRegFile[per_tc_regs[i]].resize(numThreads);
155 for (int j = 0; j < miscRegFile[i].size(); j++)
156 miscRegFile[i][j] = 0;
416 TCBindReg tcBind = miscRegFile[MISCREG_TC_BIND][tid];
427 miscRegFile[misc_reg][reg_sel]);
428 return miscRegFile[misc_reg][reg_sel];
442 miscRegFile[misc_re
[all...]
H A Disa.hh71 std::vector<std::vector<RegVal> > miscRegFile; member in class:MipsISA::ISA

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