Searched refs:masterPorts (Results 1 - 7 of 7) sorted by relevance

/gem5/util/tlm/src/
H A Dsim_control.cc194 if (masterPorts.find(name) == masterPorts.end()) {
195 masterPorts[name] = port;
216 if (masterPorts.find(name) == masterPorts.end()) {
221 return masterPorts.at(name);
H A Dsim_control.hh75 std::map<const std::string, SCMasterPort*> masterPorts; member in class:Gem5SystemC::Gem5SimControl
/gem5/src/mem/
H A Dxbar.cc72 for (auto m: masterPorts)
82 if (if_name == "master" && idx < masterPorts.size()) {
84 return *masterPorts[idx];
86 return *masterPorts[defaultPortID];
347 masterPorts[master_port_id]->getPeer());
375 AddrRangeList ranges = masterPorts[master_port_id]->getAddrRanges();
397 AddrRangeList ranges = masterPorts[master_port_id]->getAddrRanges();
408 masterPorts[master_port_id]->getPeer(),
409 masterPorts[conflict_id]->getPeer());
542 .init(slavePorts.size(), masterPorts
[all...]
H A Dnoncoherent_xbar.cc66 masterPorts.push_back(bp);
74 defaultPortID = masterPorts.size();
78 masterPorts.push_back(bp);
147 bool success = masterPorts[master_port_id]->sendTimingReq(pkt);
183 MasterPort *src_port = masterPorts[master_port_id];
265 auto master = masterPorts[master_port_id];
312 masterPorts[dest_id]->sendFunctional(pkt);
H A Dcoherent_xbar.cc73 masterPorts.push_back(bp);
83 defaultPortID = masterPorts.size();
87 masterPorts.push_back(bp);
201 if (!masterPorts[master_port_id]->tryTiming(pkt)) {
286 success = masterPorts[master_port_id]->sendTimingReq(pkt);
443 MasterPort *src_port = masterPorts[master_port_id];
505 masterPorts[master_port_id]->name(), pkt->print());
534 __func__, masterPorts[master_port_id]->name(), pkt->print(),
634 *masterPorts[dest_port_id]);
638 masterPorts[dest_port_i
[all...]
H A Dhmc_controller.cc88 bool success = masterPorts[master_port_id]->sendTimingReq(pkt);
H A Dxbar.hh381 std::vector<MasterPort*> masterPorts; member in class:BaseXBar

Completed in 8 milliseconds