Searched refs:m_input_unit (Results 1 - 4 of 4) sorted by relevance

/gem5/src/mem/ruby/network/garnet2.0/
H A DSwitchAllocator.cc56 m_input_unit = m_router->get_inputUnit_ref();
121 if (m_input_unit[inport]->need_stage(invc, SA_,
126 int outport = m_input_unit[inport]->get_outport(invc);
127 int outvc = m_input_unit[inport]->get_outvc(invc);
187 int outvc = m_input_unit[inport]->get_outvc(invc);
194 flit *t_flit = m_input_unit[inport]->getTopFlit(invc);
205 m_input_unit[inport]->get_direction()),
233 assert(!(m_input_unit[inport]->isReady(invc,
237 m_input_unit[inport]->set_vc_idle(invc,
242 m_input_unit[inpor
[all...]
H A DRouter.cc62 m_input_unit.clear();
68 deletePointers(m_input_unit);
90 for (int inport = 0; inport < m_input_unit.size(); inport++) {
91 m_input_unit[inport]->wakeup();
115 int port_num = m_input_unit.size();
123 m_input_unit.push_back(input_unit);
158 return m_input_unit[inport]->get_direction();
225 for (int i = 0; i < m_input_unit.size(); i++) {
226 m_buffer_reads += m_input_unit[i]->get_buf_read_activity(j);
227 m_buffer_writes += m_input_unit[
[all...]
H A DRouter.hh79 int get_num_inports() { return m_input_unit.size(); }
89 std::vector<InputUnit *>& get_inputUnit_ref() { return m_input_unit; }
124 std::vector<InputUnit *> m_input_unit; member in class:Router
H A DSwitchAllocator.hh86 std::vector<InputUnit *> m_input_unit; member in class:SwitchAllocator

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