Searched refs:m_abs_cntrl_vec (Results 1 - 2 of 2) sorted by relevance

/gem5/src/mem/ruby/system/
H A DRubySystem.cc89 m_abs_cntrl_vec.push_back(cntrl);
109 for (int cntrl = 0; cntrl < m_abs_cntrl_vec.size(); cntrl++) {
110 sequencer_map.push_back(m_abs_cntrl_vec[cntrl]->getCPUSequencer());
118 for (int cntrl = 0; cntrl < m_abs_cntrl_vec.size(); cntrl++) {
142 for (int cntrl = 0; cntrl < m_abs_cntrl_vec.size(); cntrl++) {
143 m_abs_cntrl_vec[cntrl]->recordCacheTrace(cntrl, m_cache_recorder);
405 int num_controllers = m_abs_cntrl_vec.size();
418 access_perm = m_abs_cntrl_vec[i]-> getAccessPermission(line_address);
447 access_perm = m_abs_cntrl_vec[i]->getAccessPermission(line_address);
449 m_abs_cntrl_vec[
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H A DRubySystem.hh134 std::vector<AbstractController *> m_abs_cntrl_vec; member in class:RubySystem

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