Searched refs:m5 (Results 1 - 25 of 488) sorted by relevance

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/gem5/tests/
H A Dhalt.sh0 m5 exit
/gem5/configs/boot/
H A Dhalt.sh0 m5 exit
H A Dmutex-test.rcS4 /sbin/m5 resetstats
6 /sbin/m5 exit
H A Dgzip.rcS5 /sbin/m5 checkpoint 0 0
6 /sbin/m5 checkpoint 100000000 200000000
8 /sbin/m5 loadsymbol
10 /sbin/m5 resetstats
12 /sbin/m5 exit
H A Dammp.rcS5 /sbin/m5 checkpoint 0 0
6 /sbin/m5 checkpoint 100000000 200000000
8 /sbin/m5 loadsymbol
10 /sbin/m5 resetstats
12 /sbin/m5 exit
H A Dequake.rcS5 /sbin/m5 checkpoint 0 0
6 /sbin/m5 checkpoint 100000000 200000000
8 /sbin/m5 loadsymbol
10 /sbin/m5 resetstats
12 /sbin/m5 exit
/gem5/src/base/
H A DGraphics.py38 from m5.SimObject import SimObject
39 from m5.params import *
/gem5/src/dev/arm/
H A DAbstractNVM.py39 from m5.params import *
40 from m5.proxy import *
41 from m5.SimObject import SimObject
/gem5/src/cpu/kvm/
H A DKvmVM.py38 from m5.params import *
39 from m5.proxy import *
41 from m5.SimObject import SimObject
/gem5/src/arch/generic/
H A DISACommon.py38 from m5.params import *
39 from m5.proxy import *
40 from m5.SimObject import SimObject
/gem5/src/arch/sparc/
H A DSparcNativeTrace.py29 from m5.SimObject import SimObject
30 from m5.params import *
32 from m5.objects.CPUTracers import NativeTrace
/gem5/src/arch/x86/
H A DX86NativeTrace.py29 from m5.SimObject import SimObject
30 from m5.params import *
32 from m5.objects.CPUTracers import NativeTrace
/gem5/src/dev/x86/
H A DI8237.py29 from m5.params import *
30 from m5.proxy import *
31 from m5.objects.Device import BasicPioDevice
H A DI8254.py29 from m5.params import *
30 from m5.proxy import *
31 from m5.objects.Device import BasicPioDevice
32 from m5.objects.IntPin import IntSourcePin
/gem5/src/mem/ruby/structures/
H A DLRUReplacementPolicy.py32 from m5.params import *
33 from m5.SimObject import SimObject
34 from m5.objects.ReplacementPolicy import ReplacementPolicy
/gem5/src/arch/arm/kvm/
H A DKvmGic.py38 from m5.params import *
39 from m5.proxy import *
41 from m5.objects.Gic import GicV2
H A DArmV8KvmCPU.py38 from m5.params import *
39 from m5.objects.BaseArmKvmCPU import BaseArmKvmCPU
H A DArmKvmCPU.py38 from m5.params import *
39 from m5.objects.BaseKvmCPU import BaseKvmCPU
/gem5/src/mem/ruby/network/simple/
H A DSimpleLink.py30 from m5.params import *
31 from m5.proxy import *
32 from m5.SimObject import SimObject
33 from m5.objects.BasicLink import BasicIntLink, BasicExtLink
/gem5/src/learning_gem5/part2/
H A DSimpleObject.py30 from m5.params import *
31 from m5.SimObject import SimObject
/gem5/configs/example/
H A Dsc_main.py32 import m5
33 from m5.objects import SystemC_Kernel, Root
40 m5.systemc.sc_main(*sys.argv)
42 m5.instantiate(None)
44 cause = m5.simulate(m5.MaxTick).getCause()
46 result = m5.systemc.sc_main_result()
48 m5.util.panic('sc_main return code was %d.' % result.code)
/gem5/src/cpu/
H A DDummyChecker.py38 from m5.params import *
39 from m5.objects.CheckerCPU import CheckerCPU
/gem5/src/cpu/o3/
H A DO3Checker.py29 from m5.params import *
30 from m5.objects.CheckerCPU import CheckerCPU
/gem5/src/mem/
H A DHMCController.py41 from m5.params import *
42 from m5.objects.XBar import *
/gem5/src/unittest/
H A Dstattestmain.py3 import m5.stats
8 m5.stats.initSimStats()
9 m5.stats.addStatVisitor("cout")
12 m5.stats.enable()
15 m5.stats.reset()
19 m5.stats.dump()

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