Searched refs:lane (Results 1 - 10 of 10) sorted by relevance

/gem5/src/arch/hsail/insts/
H A Dpseudo_inst.cc87 for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
88 if (mask[lane]) {
89 int src_val0 = src1.get<int>(w, lane, 0);
185 for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
186 if (mask[lane]) {
187 int src_val1 = src1.get<int>(w, lane,
[all...]
H A Dmem_impl.hh66 for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
67 if (mask[lane]) {
68 this->dest.set(w, lane, addr_vec[lane]);
123 calcPrivAddr(Addr addr, Wavefront *w, int lane, GPUStaticInst *i) argument
136 lane * se->size;
152 Addr ret = addr_div8 * 8 * w->computeUnit->wfSize() + lane * 8 +
190 for (int lane
[all...]
H A Dmain.cc137 for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
138 if (mask[lane]) {
139 w->initMask[lane] = 0;
H A Dbranch.hh283 for (unsigned int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
284 true_mask[lane] = cond.get<bool>(w, lane) & curr_mask[lane];
/gem5/src/arch/hsail/
H A Doperand.hh156 get(Wavefront *w, int lane) argument
168 read<uint32_t>(vgprIdx, lane)) & 0xff;
173 read<uint32_t>(vgprIdx, lane)) & 0xffff;
178 read<OperandType>(vgprIdx, lane);
190 getTarget(Wavefront *w, int lane) argument
192 return get<uint32_t>(w, lane);
196 void set(Wavefront *w, int lane, OperandType &val);
202 SRegOperand::set(Wavefront *w, int lane, OperandType &val) argument
204 DPRINTF(GPUReg, "CU%d, WF[%d][%d], lane %d: $s%d <- %d\n",
205 w->computeUnit->cu_id, w->simdId, w->wfSlotId, lane, regId
215 set(Wavefront *w, int lane, uint64_t &val) argument
261 get(Wavefront *w, int lane) argument
273 set(Wavefront *w, int lane, OperandType &val) argument
325 get(Wavefront *w, int lane) argument
334 set(Wavefront *w, int lane, OperandType &val) argument
382 get(Wavefront *w, int lane) argument
474 get(Wavefront *w, int lane) argument
689 calcLane(Wavefront *w, int lane) argument
723 calcLane(Wavefront *w, int lane) argument
771 get(Wavefront *w, int lane, int arg_idx) argument
778 set(Wavefront *w, int lane, OperandType val) argument
[all...]
H A Doperand.cc459 LabelOperand::getTarget(Wavefront *w, int lane) argument
/gem5/src/gpu-compute/
H A Dwavefront.hh116 getLaneOffset(int lane, int addr) argument
118 return addr * wfSize + sizeof(CType) * lane;
134 getLaneAddr(int lane, int addr) argument
136 return mem + getLaneOffset<CType>(lane, addr);
141 setLaneAddr(int lane, int addr, CType val) argument
143 *((CType*)(mem + getLaneOffset<CType>(lane, addr))) = val;
309 readCallArgMem(int lane, int addr) argument
311 return *((CType*)(callArgMem->getLaneAddr<CType>(lane, addr)));
316 writeCallArgMem(int lane, int addr, CType val) argument
318 callArgMem->setLaneAddr<CType>(lane, add
[all...]
H A Dwavefront.cc777 Wavefront::waitingAtBarrier(int lane) argument
779 return barCnt[lane] < maxBarCnt;
834 Wavefront::execMask(int lane) const
836 return reconvergenceStack.back()->execMask[lane];
892 for (int lane = 0; lane < wf_size; lane++) {
894 read<uint32_t>(vgprIdx,lane);
901 for (int lane = 0; lane < wf_siz
[all...]
/gem5/src/arch/arm/insts/
H A Dmacromem.cc558 RegIndex rm, unsigned lane) :
662 machInst, vd * 2, ufp0, inc * 2, lane);
671 machInst, vd * 2, ufp0, inc * 2, lane);
680 machInst, vd * 2, ufp0, inc * 2, lane);
698 machInst, vd * 2, ufp0, inc * 2, lane);
707 machInst, vd * 2, ufp0, inc * 2, lane);
716 machInst, vd * 2, ufp0, inc * 2, lane);
735 machInst, vd * 2, ufp0, inc * 2, lane);
744 machInst, vd * 2, ufp0, inc * 2, lane);
753 machInst, vd * 2, ufp0, inc * 2, lane);
554 VldSingleOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, bool all, unsigned elems, RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, uint32_t size, uint32_t align, RegIndex rm, unsigned lane) argument
917 VstSingleOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, bool all, unsigned elems, RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, uint32_t size, uint32_t align, RegIndex rm, unsigned lane) argument
[all...]
H A Dmacromem.hh148 unsigned lane; member in class:ArmISA::MicroNeonMixLaneOp
154 lane(_lane)
183 uint8_t eSize, dataSize, numStructElems, lane, step; member in class:ArmISA::MicroNeonMixLaneOp64
193 lane(_lane), step(_step), replicate(_replicate)
509 uint32_t align, RegIndex rm, unsigned lane);
529 uint32_t align, RegIndex rm, unsigned lane);

Completed in 26 milliseconds