Searched refs:inv (Results 1 - 17 of 17) sorted by relevance

/gem5/ext/dsent/model/electrical/
H A DBroadcastHTree.cc275 StdCell* inv = getTechModel()->getStdCellLib()->createStdCell("INV", "LeafDriver0"); local
276 inv->construct();
277 inv->getNet("Y")->addDownstreamNode(m_leaf_load_);
278 inv->setDrivingStrengthIdx(min_driving_strength_idx);
279 m_leaf_drivers_.push_back(inv);
318 inv = getTechModel()->getStdCellLib()->createStdCell("INV", "LeafDriver" + (String)(curr_driver+1));
319 inv->construct();
320 inv->getNet("Y")->addDownstreamNode(m_leaf_drivers_[curr_driver]->getNet("A"));
321 inv->setDrivingStrengthIdx(min_driving_strength_idx);
322 m_leaf_drivers_.push_back(inv);
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H A DDecoder.cc245 ElectricalModel* inv = (ElectricalModel*)getSubInstance("INV_" + (String)i); local
246 propagatePortTransitionInfo(inv, "A", nand2, "Y");
247 inv->use();
249 propagatePortTransitionInfo("Out" + (String)i, inv, "Y");
/gem5/ext/dsent/model/std_cells/
H A DStdCellLib.cc132 StdCell* inv = createStdCell("INV", "CachedINV"); local
133 inv->cacheStdCell(this, cell_sizes[i].toDouble());
134 delete inv;
/gem5/ext/mcpat/
H A Dlogic.cc116 + cmos_Isub_leakage(WSelEnn, WSelEnp, 1, inv)*2*3//for each grant there are two inverters, there are 3 grant sIsubnals
123 + cmos_Ig_leakage(WSelEnn, WSelEnp, 1, inv)*2*3//for each grant there are two inverters, there are 3 grant signals
528 leakage = area_t *(g_tp.scaling_factor.core_tx_density)*cmos_Isub_leakage(5*g_tp.min_w_nmos_, 5*g_tp.min_w_nmos_*pmos_to_nmos_sizing_r, 1, inv)*g_tp.peri_global.Vdd/2;//unit W
529 gate_leakage = area_t *(g_tp.scaling_factor.core_tx_density)*cmos_Ig_leakage(5*g_tp.min_w_nmos_, 5*g_tp.min_w_nmos_*pmos_to_nmos_sizing_r, 1, inv)*g_tp.peri_global.Vdd/2;//unit W
540 leakage = area_t *(g_tp.scaling_factor.core_tx_density)*cmos_Isub_leakage(20*g_tp.min_w_nmos_, 20*g_tp.min_w_nmos_*pmos_to_nmos_sizing_r, 1, inv)*g_tp.peri_global.Vdd/2;//unit W
541 gate_leakage = area_t*(g_tp.scaling_factor.core_tx_density)*cmos_Ig_leakage(20*g_tp.min_w_nmos_, 20*g_tp.min_w_nmos_*pmos_to_nmos_sizing_r, 1, inv)*g_tp.peri_global.Vdd/2;
551 leakage = area_t *(g_tp.scaling_factor.core_tx_density)*cmos_Isub_leakage(20*g_tp.min_w_nmos_, 20*g_tp.min_w_nmos_*pmos_to_nmos_sizing_r, 1, inv)*g_tp.peri_global.Vdd/2;//unit W
552 gate_leakage = area_t*(g_tp.scaling_factor.core_tx_density)*cmos_Ig_leakage(20*g_tp.min_w_nmos_, 20*g_tp.min_w_nmos_*pmos_to_nmos_sizing_r, 1, inv)*g_tp.peri_global.Vdd/2;
572 leakage = area_t *(g_tp.scaling_factor.core_tx_density)*cmos_Isub_leakage(5*g_tp.min_w_nmos_, 5*g_tp.min_w_nmos_*pmos_to_nmos_sizing_r, 1, inv)*g_tp.peri_global.Vdd/2;//unit W
573 gate_leakage = area_t *(g_tp.scaling_factor.core_tx_density)*cmos_Ig_leakage(5*g_tp.min_w_nmos_, 5*g_tp.min_w_nmos_*pmos_to_nmos_sizing_r, 1, inv)*g_t
[all...]
H A Dmemoryctrl.cc133 cmos_Isub_leakage(NMOS_sizing, PMOS_sizing, 1, inv) *
137 cmos_Ig_leakage(NMOS_sizing, PMOS_sizing, 1, inv) *
166 cmos_Isub_leakage(NMOS_sizing, PMOS_sizing, 1, inv) *
170 cmos_Ig_leakage(NMOS_sizing, PMOS_sizing, 1, inv) *
266 cmos_Isub_leakage(NMOS_sizing, PMOS_sizing, 1, inv) *
270 cmos_Ig_leakage(NMOS_sizing, PMOS_sizing, 1, inv) *
/gem5/ext/mcpat/cacti/
H A Darbiter.cc101 min_w_pmos * PTi, 1, inv);
107 min_w_pmos * PTi, 1, inv);
H A Ddecoder.cc166 cmos_Isub_leakage(w_dec_n[i], w_dec_p[i], 1, inv, is_dram);
168 cmos_Ig_leakage(w_dec_n[i], w_dec_p[i], 1, inv, is_dram);
255 cumulative_curr += cmos_Isub_leakage(w_dec_n[i], w_dec_p[i], 1, inv, is_dram);
256 cumulative_curr_Ig = cmos_Ig_leakage(w_dec_n[i], w_dec_p[i], 1, inv, is_dram);
637 leakage_L2 += cmos_Isub_leakage(w_L2_n[i], w_L2_p[i], 2, inv, is_dram_);
638 gate_leakage_L2 += cmos_Ig_leakage(w_L2_n[i], w_L2_p[i], 2, inv, is_dram_);
952 leakage_L2 += cmos_Isub_leakage(w_L2_n[i], w_L2_p[i], 2, inv, is_dram_);
953 gate_leakage_L2 += cmos_Ig_leakage(w_L2_n[i], w_L2_p[i], 2, inv, is_dram_);
1142 1, inv, is_dram_);
1145 1, inv, is_dram
[all...]
H A Dbasic_circuit.h80 inv, enumerator in enum:Gate_type
H A Dcrossbar.cc137 1, inv) * Vdd +
145 1, inv) * Vdd +
H A Dmat.cc952 1, inv, false, true) * 2;
954 double Icell_comparator = cmos_Isub_leakage(Wdummyn, Wdummyn, 1, inv,
985 1, inv, false, true) * 2;
986 double Ig_cell_comparator = cmos_Ig_leakage(Wdummyn, Wdummyn, 1, inv,
1084 g_tp.sram.cell_pmos_w, 1, inv, false,
1096 g_tp.sram.cell_pmos_w, 1, inv, false,
1299 inv, is_dram) * g_tp.peri_global.Vdd;
1302 inv) * g_tp.peri_global.Vdd;
1319 inv) * g_tp.peri_global.Vdd;
1322 inv) * g_t
[all...]
H A Dwire.cc464 * The load capacitance of this inv depends on
484 4 * cmos_Isub_leakage(g_tp.min_w_nmos_, min_w_pmos, 1, inv));
488 4 * cmos_Ig_leakage(g_tp.min_w_nmos_, min_w_pmos, 1, inv));
612 repeater_scaling, 1, inv));
618 repeater_scaling, 1, inv));
771 repeater_size, 1, inv));
778 repeater_size, 1, inv));
H A Dhtree2.cc230 2, 1, inv) *
241 1, inv) *
252 2, 1, inv) *
263 1, inv) *
H A Dbasic_circuit.cc459 case inv:
568 case inv:
/gem5/src/mem/cache/prefetch/
H A Dbase.cc131 bool inv = pkt->isInvalidate(); local
138 if (!fetch && !read && inv) return false;
/gem5/src/dev/arm/
H A Dgic_v3_its.hh504 void inv(Yield &yield, CommandEntry &command);
H A Dgic_v3_its.cc294 COMMAND(INV, &ItsCommand::inv),
497 ItsCommand::inv(Yield &yield, CommandEntry &command) function in class:ItsCommand
/gem5/src/arch/x86/regs/
H A Dmisc.hh810 Bitfield<23> inv; // Invert mask member in namespace:X86ISA

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