Searched refs:inst_port (Results 1 - 2 of 2) sorted by relevance

/gem5/src/learning_gem5/part2/
H A DSimpleMemobj.py37 inst_port = SlavePort("CPU side port, receives requests") variable in class:SimpleMemobj
/gem5/configs/learning_gem5/part2/
H A Dsimple_memobj.py63 system.cpu.icache_port = system.memobj.inst_port

Completed in 4 milliseconds