Searched refs:elems (Results 1 - 6 of 6) sorted by relevance

/gem5/util/minorview/
H A Dparse.py44 elems = re.split(',', names)
47 for elem in elems:
H A Dmodel.py116 elems = m.groups()
118 if elems[0] is not None:
123 self.threadId = seqnum_from_string(elems[1])
124 self.streamSeqNum = seqnum_from_string(elems[2])
125 self.predictionSeqNum = seqnum_from_string(elems[3])
126 self.lineSeqNum = seqnum_from_string(elems[4])
127 self.fetchSeqNum = seqnum_from_string(elems[6])
128 self.execSeqNum = seqnum_from_string(elems[8])
255 def elems(self): member in class:ColourPattern
329 def elems(sel member in class:TwoDColours
361 def elems(self): member in class:FrameColours
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H A Dview.py203 def make_bar(elems):
206 for widget, signal, handler in elems:
481 # blocks = event.visuals[picChar].elems()
/gem5/src/arch/arm/insts/
H A Dmacromem.cc460 unsigned elems, RegIndex rn, RegIndex vd, unsigned regs,
465 assert(regs % elems == 0);
469 bool deinterleave = (elems > 1);
472 if (deinterleave) numMicroops += (regs / elems);
515 switch (elems) {
555 OpClass __opClass, bool all, unsigned elems,
562 assert(regs % elems == 0);
565 unsigned loadSize = eBytes * elems;
575 numMicroops += (regs / elems);
652 switch (elems) {
459 VldMultOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, unsigned elems, RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, uint32_t size, uint32_t align, RegIndex rm) argument
554 VldSingleOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, bool all, unsigned elems, RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, uint32_t size, uint32_t align, RegIndex rm, unsigned lane) argument
822 VstMultOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, unsigned elems, RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, uint32_t size, uint32_t align, RegIndex rm) argument
917 VstSingleOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, bool all, unsigned elems, RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, uint32_t size, uint32_t align, RegIndex rm, unsigned lane) argument
[all...]
H A Dmacromem.hh499 unsigned elems, RegIndex rn, RegIndex vd, unsigned regs,
507 bool all, unsigned elems, RegIndex rn, RegIndex vd,
527 bool all, unsigned elems, RegIndex rn, RegIndex vd,
/gem5/src/arch/
H A Disa_parser.py679 (elem_spec, dflt_elem_ext, zeroing) = self.elems[elem_name]
716 (elem_spec, dflt_elem_ext, zeroing) = self.elems[elem_name]
753 (elem_spec, dflt_elem_ext, zeroing) = self.elems[elem_name]
2555 # (for elems of vector)
2562 elems = elem_spec
2563 attrList.append('elems')
2587 # Add the elems defined in the vector operands and
2591 if hasattr(self.operandNameMap[op], 'elems'):
2592 for elem in self.operandNameMap[op].elems.keys():

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