Searched refs:dma (Results 1 - 10 of 10) sorted by relevance

/gem5/src/dev/pci/
H A DCopyEngine.py38 dma = VectorMasterPort("Copy engine DMA port") variable in class:CopyEngine
/gem5/configs/example/
H A Druby_mem_test.py58 parser.add_option("--num-dmas", type="int", default=0, help="# of dma testers")
126 for (i, dma) in enumerate(dmas):
127 dma_ports.append(dma.test)
H A Dapu_se.py513 dispatcher.dma = system.piobus.slave
/gem5/src/dev/x86/
H A DSouthBridge.py63 dma1 = Param.I8237(_dma1, "The first dma controller")
105 if dma_ports.count(self.ide.dma) == 0:
106 self.ide.dma = bus.slave
/gem5/src/dev/
H A DDevice.py85 dma = MasterPort("DMA port") variable in class:DmaDevice
102 a dma device and the iommu.
/gem5/configs/common/
H A DFSConfig.py105 # Store the dma devices for later connection to dma ruby ports.
107 self._dma_ports = [self.tsunami.ide.dma, self.tsunami.ethernet.dma]
119 self.tsunami.ide.dma = self.iobus.slave
120 self.tsunami.ethernet.dma = self.iobus.slave
423 self.malta.ide.dma = self.iobus.slave
425 self.malta.ethernet.dma = self.iobus.slave
492 # add the ide to the list of dma devices that later need to attach to
493 # dma controller
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/gem5/src/dev/arm/
H A DSMMUv3.py191 be either a dma port (if the SMMU is attached directly to a
192 dma device), or to a master port (this is the case where the SMMU
203 elif hasattr(device, "dma"):
204 slave_interface.slave = device.dma
H A DGic.py182 dma = MasterPort("DMA port") variable in class:Gicv3Its
H A DRealView.py126 # on/off the fdt dma-coherent flag when doing dtb autogeneration
204 node.append(FdtProperty("dma-coherent"))
556 if hasattr(device, "dma"):
558 device.dma = bus.slave
560 dma_ports.append(device.dma)
700 self.clcd.dma = bus.slave
704 self.cf_ctrl.dma = bus.slave
/gem5/tests/configs/
H A Dgpu-ruby.py331 dispatcher.dma = system.piobus.slave

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