Searched refs:divw (Results 1 - 4 of 4) sorted by relevance

/gem5/tests/test-progs/asmtest/src/riscv/isa/rv64um/
H A Ddivw.S4 # divw.S
7 # Test divw instruction.
20 TEST_RR_OP( 2, divw, 3, 20, 6 );
21 TEST_RR_OP( 3, divw, -3, -20, 6 );
22 TEST_RR_OP( 4, divw, -3, 20, -6 );
23 TEST_RR_OP( 5, divw, 3, -20, -6 );
25 TEST_RR_OP( 6, divw, -1<<31, -1<<31, 1 );
26 TEST_RR_OP( 7, divw, -1<<31, -1<<31, -1 );
28 TEST_RR_OP( 8, divw, -1, -1<<31, 0 );
29 TEST_RR_OP( 9, divw,
[all...]
/gem5/tests/test-progs/insttest/src/riscv/
H A Drv64m.cpp102 []{return M::divw(0x7FFFFFFFFFFFFFC5LL, 0xFFFFFFFF00000008LL);},
103 "divw, truncate");
104 expect<int64_t>(-1, []{return M::divw(65535, 0);}, "divw/0");
106 []{return M::divw(numeric_limits<int32_t>::min(), -1);},
107 "divw, overflow");
H A Drv64m.h113 divw(int64_t rs1, int64_t rs2) function in namespace:M
116 ROP("divw", rd, rs1, rs2);
/gem5/tests/test-progs/asmtest/src/riscv/env/
H A Dencoding.h1039 DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW)

Completed in 15 milliseconds