Searched refs:divuw (Results 1 - 4 of 4) sorted by relevance
| /gem5/tests/test-progs/asmtest/src/riscv/isa/rv64um/ |
| H A D | divuw.S | 4 # divuw.S
7 # Test divuw instruction.
20 TEST_RR_OP( 2, divuw, 3, 20, 6 );
21 TEST_RR_OP( 3, divuw, 715827879, -20 << 32 >> 32, 6 );
22 TEST_RR_OP( 4, divuw, 0, 20, -6 );
23 TEST_RR_OP( 5, divuw, 0, -20, -6 );
25 TEST_RR_OP( 6, divuw, -1<<31, -1<<31, 1 );
26 TEST_RR_OP( 7, divuw, 0, -1<<31, -1 );
28 TEST_RR_OP( 8, divuw, -1, -1<<31, 0 );
29 TEST_RR_OP( 9, divuw,
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| /gem5/tests/test-progs/insttest/src/riscv/ |
| H A D | rv64m.cpp | 111 []{return M::divuw(0x7FFFFFFFFFFFFFC5LL, 0xFFFFFFFF00000008LL);},
112 "divuw, truncate");
114 []{return M::divuw(65535, 0);}, "divuw/0");
116 []{return M::divuw(numeric_limits<int32_t>::min(), -1);},
117 "divuw, \"overflow\"");
119 []{return M::divuw(numeric_limits<uint32_t>::max(), 1);},
120 "divuw, sign extend");
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| H A D | rv64m.h | 121 divuw(uint64_t rs1, uint64_t rs2) function in namespace:M
124 ROP("divuw", rd, rs1, rs2);
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| /gem5/tests/test-progs/asmtest/src/riscv/env/ |
| H A D | encoding.h | 1040 DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW)
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