Searched refs:decodeSave (Results 1 - 12 of 12) sorted by relevance
| /gem5/src/arch/alpha/ |
| H A D | stacktrace.hh | 72 bool decodeSave(MachInst inst, int ®, int &disp);
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| H A D | stacktrace.cc | 278 StackTrace::decodeSave(MachInst inst, int ®, int &disp) function in class:AlphaISA::StackTrace
323 } else if (decodeSave(inst, reg, disp)) {
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| /gem5/src/arch/arm/ |
| H A D | stacktrace.hh | 74 bool decodeSave(MachInst inst, int ®, int &disp);
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| H A D | stacktrace.cc | 147 StackTrace::decodeSave(MachInst inst, int ®, int &disp) function in class:ArmISA::StackTrace
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| /gem5/src/arch/mips/ |
| H A D | stacktrace.hh | 71 bool decodeSave(MachInst inst, int ®, int &disp);
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| H A D | stacktrace.cc | 169 StackTrace::decodeSave(MachInst inst, int ®, int &disp) function in class:StackTrace
213 } else if (decodeSave(inst, reg, disp)) {
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| /gem5/src/arch/x86/ |
| H A D | stacktrace.hh | 71 bool decodeSave(MachInst inst, int ®, int &disp);
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| H A D | stacktrace.cc | 148 StackTrace::decodeSave(MachInst inst, int ®, int &disp) function in class:X86ISA::StackTrace
176 } else if (decodeSave(inst, reg, disp)) {
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| /gem5/src/arch/riscv/ |
| H A D | stacktrace.cc | 104 StackTrace::decodeSave(MachInst inst, int ®, int &disp) function in class:RiscvISA::StackTrace
106 panic("StackTrace::decodeSave not implemented.\n");
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| H A D | stacktrace.hh | 67 bool decodeSave(MachInst inst, int ®, int &disp);
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| /gem5/src/arch/power/ |
| H A D | stacktrace.cc | 105 StackTrace::decodeSave(MachInst inst, int ®, int &disp) function in class:PowerISA::StackTrace
107 panic("StackTrace::decodeSave not implemented.\n");
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| H A D | stacktrace.hh | 67 bool decodeSave(MachInst inst, int ®, int &disp);
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