Searched refs:cycle (Results 1 - 16 of 16) sorted by relevance

/gem5/src/sim/
H A Dclocked_object.hh73 // The cycle counter value corresponding to the current value of
75 mutable Cycles cycle; member in class:Clocked
78 * Align cycle and tick to the next clock edge if not already done. When
84 // both tick and cycle are up-to-date and we are done, note
93 ++cycle;
99 // if not, we have to recalculate the cycle and tick, we
103 cycle += elapsedCycles;
119 : tick(0), cycle(0), clockDomain(clk_domain)
143 cycle = elapsedCycles;
166 * Determine the tick when a cycle begin
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/gem5/src/systemc/tests/systemc/misc/sim_tests/cycle_dw8051_demo/
H A Dcycle_model.cpp43 // ABSTRACT: cycle-accurate model based on the dw8051 architecture
55 // Then the cycle-accurate model does the following operations:
78 // used and the model automatically switches to a real cycle-accurate mode
79 // for a given number of cycle. This is implemented within the function:
82 // This cycle-accurate model implements only parts of the dw8051. The
252 i->cycle = 1;
262 i->cycle = 2;
274 i->cycle = 1;
284 i->cycle = 2;
302 i->cycle
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H A Dcycle_model.h91 /* cycle types for memory bus */
117 int cycle; // number of cycles member in struct:instr
/gem5/src/mem/
H A Ddramsim2.hh154 * Progress the controller one clock cycle.
179 * @param cycle Internal cycle count of DRAMSim2
181 void readComplete(unsigned id, uint64_t addr, uint64_t cycle);
188 * @param cycle Internal cycle count of DRAMSim2
190 void writeComplete(unsigned id, uint64_t addr, uint64_t cycle);
H A Ddramsim2.cc287 void DRAMSim2::readComplete(unsigned id, uint64_t addr, uint64_t cycle)
289 assert(cycle == divCeil(curTick() - startTick,
315 void DRAMSim2::writeComplete(unsigned id, uint64_t addr, uint64_t cycle)
317 assert(cycle == divCeil(curTick() - startTick,
/gem5/ext/systemc/src/sysc/tracing/
H A Dsc_trace_file_base.cpp84 // values only after the first delta cycle, though.
118 // delta cycle is traced at the end of an update phase
119 cycle( simcontext()->get_status() == SC_END_OF_UPDATE );
H A Dsc_vcd_trace.h197 // Write trace info for cycle.
198 void cycle(bool delta_cycle);
H A Dsc_wif_trace.h192 // Write trace info for cycle.
193 void cycle(bool delta_cycle);
H A Dsc_trace.h162 // Write trace info for cycle
163 virtual void cycle( bool delta_cycle ) = 0;
358 // Turn on/off delta cycle tracing on trace file `tf'.
359 // Default is to turn on delta cycle tracing.
H A Dsc_wif_trace.cpp1779 wif_trace_file::cycle(bool this_is_a_delta_cycle) function in class:sc_core::wif_trace_file
1802 delta_units_low++; // Increment time for delta cycle simulation
H A Dsc_vcd_trace.cpp1906 vcd_trace_file::cycle(bool this_is_a_delta_cycle) function in class:sc_core::vcd_trace_file
1965 // Not a delta cycle and time has not progressed
1982 // Not a delta cycle and time has gone backward
/gem5/ext/sst/
H A Dgem5.cc167 gem5Component::clockTick(Cycle_t cycle) argument
169 dbg.output(CALL_INFO, "Cycle %lu\n", cycle);
/gem5/ext/pybind11/tests/
H A Dtest_methods_and_attributes.py316 i1.cycle = i2
317 i2.cycle = i1
/gem5/ext/systemc/src/sysc/kernel/
H A Dsc_simcontext.cpp486 // | one or more "delta" cycles. Each delta cycle consists of an evaluation,
494 // | that are sensitive to those notifications. At that point a delta cycle
498 // | once = true if only one delta cycle is to be performed.
587 trace_cycle( /* delta cycle? */ true );
649 sc_simcontext::cycle( const sc_time& t) function in class:sc_core::sc_simcontext
658 trace_cycle( /* delta cycle? */ false );
844 // run the delta cycle loop
931 trace_cycle( /* delta cycle? */ false );
1029 // cycle and performs whatever updates are pending.
1030 // SC_STOP_FINISH_DELTA - finishes the current delta cycle
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H A Dsc_simcontext.h177 void cycle( const sc_time& );
899 // event_occurred() method to hide how delta cycle comparisions are done within
/gem5/tests/test-progs/asmtest/src/riscv/env/
H A Dencoding.h214 #define rdcycle() read_csr(cycle)
1246 DECLARE_CSR(cycle, CSR_CYCLE)

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