Searched refs:cr0 (Results 1 - 13 of 13) sorted by relevance

/gem5/src/arch/x86/
H A Dprocess.cc400 CR0 cr0 = 0; local
401 cr0.pg = 1; // Turn on paging.
402 cr0.cd = 0; // Don't disable caching.
403 cr0.nw = 0; // This is bit is defined to be ignored.
404 cr0.am = 1; // No alignment checking
405 cr0.wp = 1; // Supervisor mode can write read only pages
406 cr0.ne = 1;
407 cr0.et = 1; // This should always be 1
408 cr0.ts = 0; // We don't do task switching, so causing fp exceptions
410 cr0
617 CR0 cr0 = 0; local
737 CR0 cr0 = 0; local
[all...]
H A Dsystem.cc263 CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0); local
265 cr0.pg = 0;
266 tc->setMiscReg(MISCREG_CR0, cr0);
268 cr0.pe = 1;
269 tc->setMiscReg(MISCREG_CR0, cr0);
293 cr0.pg = 1;
294 tc->setMiscReg(MISCREG_CR0, cr0);
H A Disa.hh55 void updateHandyM5Reg(Efer efer, CR0 cr0,
H A Disa.cc44 ISA::updateHandyM5Reg(Efer efer, CR0 cr0, argument
57 if (cr0.pe) {
67 m5reg.paging = cr0.pg;
68 m5reg.prot = cr0.pe;
H A Dfaults.cc194 CR0 cr0 = tc->readMiscReg(MISCREG_CR0); local
196 newCR0.cd = cr0.cd;
197 newCR0.nw = cr0.nw;
H A Dtlb.cc392 CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0); local
393 bool badWrite = (!entry->writable && (inUser || cr0.wp));
/gem5/src/arch/power/
H A Dmiscregs.hh47 SubBitUnion(cr0, 31, 28)
52 EndSubBitUnion(cr0)
H A Dprocess.cc295 cr.cr0.so = 0;
297 cr.cr0.so = 1;
/gem5/src/dev/arm/
H A Dsmmu_v3.cc626 case offsetof(SMMURegs, cr0):
628 regs.cr0 = regs.cr0ack = pkt->getLE<uint32_t>();
644 if (regs.cr0 & CR0_CMDQEN_MASK) {
668 if (regs.cr0 & CR0_CMDQEN_MASK) {
H A Dsmmu_v3_defs.hh116 uint32_t cr0; // 0x0020 member in struct:SMMURegs::__anon15
H A Dsmmu_v3_transl.cc162 if (!(smmu.regs.cr0 & CR0_SMMUEN_MASK)) {
/gem5/src/gpu-compute/
H A Dgpu_tlb.cc840 CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0); local
841 bool badWrite = (!entry->writable && (inUser || cr0.wp));
1134 CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0); local
1136 bool badWrite = (!tlb_entry->writable && (inUser || cr0.wp));
/gem5/src/cpu/kvm/
H A Dx86_cpu.cc126 APPLY_SREG(cr0, MISCREG_CR0); \
439 if (!(sregs.cr0 & 1) && seg.dpl != 0)

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