| /gem5/src/mem/ |
| H A D | mem_checker.cc | 59 if (complete != TICK_FUTURE) {
61 assert(_start < complete); // should open a new write cluster, instead;
64 complete = TICK_FUTURE;
78 warn("Could not locate write transaction: serial = %d, complete = %d\n",
84 assert(it->second.complete == TICK_FUTURE);
85 it->second.complete = _complete;
93 // All writes have completed, this cluster is now complete and will be
96 // Note that we cannot simply keep updating complete, because that would
99 complete = completeMax;
112 // This write cluster is now complete, an
130 inExpectedData(Tick start, Tick complete, uint8_t data) argument
223 completeRead(MemChecker::Serial serial, Tick complete, uint8_t data) argument
265 completeWrite(MemChecker::Serial serial, Tick complete) argument
298 completeRead(MemChecker::Serial serial, Tick complete, Addr addr, size_t size, uint8_t *data) argument
[all...] |
| H A D | mem_checker.hh | 113 start(_start), complete(_complete),
120 Tick complete; //!< Completion tick member in class:MemChecker::Transaction
145 : start(TICK_FUTURE), complete(TICK_FUTURE),
178 bool isComplete() const { return complete != TICK_FUTURE; }
182 Tick complete; //!< Completion of last write in cluster member in class:MemChecker::WriteCluster
211 // The initial transaction has start == complete == TICK_INITIAL,
246 * @param complete End time of transaction to validate.
251 bool inExpectedData(Tick start, Tick complete, uint8_t data);
257 * @param complete When the read got a response.
260 bool completeRead(Serial serial, Tick complete, uint8_
545 completeWrite(MemChecker::Serial serial, Tick complete, Addr addr, size_t size) argument
[all...] |
| /gem5/src/arch/arm/ |
| H A D | stage2_lookup.hh | 73 bool complete; member in class:ArmISA::Stage2LookUp
83 fault(NoFault), complete(false), selfDelete(false)
96 bool isComplete() const { return complete; }
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| H A D | stage2_lookup.cc | 175 complete = true;
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| /gem5/src/base/ |
| H A D | chunk_generator.hh | 116 unsigned complete() const { return curAddr - startAddr; } function in class:ChunkGenerator
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| /gem5/util/batch/ |
| H A D | job.py | 242 complete = date() variable
243 print '\njob complete... %s' % complete
244 jobdir.echofile('.%s' % status, complete)
246 jobdir.setstatus('%s on %s' % (status, complete))
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| /gem5/util/pbs/ |
| H A D | job.py | 237 complete = date() variable
238 print '\njob complete... %s' % complete
239 jobdir.echofile('.%s' % status, complete)
241 jobdir.setstatus('%s on %s' % (status, complete))
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| /gem5/ext/systemc/src/sysc/communication/ |
| H A D | sc_port.cpp | 136 bool complete; member in struct:sc_core::sc_bind_info
154 complete( false ),
455 if( m_bind_info->complete ) {
487 // complete static sensitivity for methods
497 // complete static sensitivity for threads
554 m_bind_info->complete = true;
568 assert( m_bind_info != 0 && m_bind_info->complete );
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| /gem5/tests/test-progs/asmtest/src/riscv/isa/rv64si/ |
| H A D | csr.S | 117 # Note that since the test didn't complete, TESTNUM is smaller by 1.
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| /gem5/system/alpha/console/ |
| H A D | dbmentry.S | 172 ldq_l a1,0(a0) # interlock complete lock state
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| /gem5/src/dev/storage/ |
| H A D | ide_disk.cc | 453 assert(dmaReadCG->complete() < MAX_DMA_SIZE);
455 &dmaReadWaitEvent, dataBuffer + dmaReadCG->complete());
536 assert(dmaWriteCG->complete() < MAX_DMA_SIZE);
538 &dmaWriteWaitEvent, dataBuffer + dmaWriteCG->complete());
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| /gem5/src/cpu/o3/ |
| H A D | lsq_unit.hh | 411 complete() function in class:LSQUnit::LQSenderState
429 complete() function in class:LSQUnit::SQSenderState
746 // This may happen if the store was not complete the
808 // complete.
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| H A D | lsq.hh | 95 /** Number of outstanding packets to complete. */
117 virtual void complete() = 0;
682 complete() function
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| H A D | lsq_unit_impl.hh | 120 /* Notify the sender state that the access is complete (for ownership
122 state->complete();
139 // atomics), so it can complete without writing back
560 // If we have a partial fault where the mem access is not complete yet
563 // mem access is complete.
801 req->complete();
802 // Instantly complete this store.
953 // Squashed instructions do not need to complete their access.
967 // If the instruction has an outstanding fault, we cannot complete
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| /gem5/src/dev/ |
| H A D | dma_device.cc | 184 pkt->dataStatic(data + gen.complete());
372 // address. Pending requests will still complete.
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| /gem5/src/cpu/minor/ |
| H A D | lsq.cc | 684 /* A request can become complete by several paths, this is a sanity
837 * the queue, not after their transfers are complete */
1069 // complete before we can issue this non-bufferable request.
1105 " data. Must wait for the store to complete\n");
1484 /* Same instruction and complete access or a store that's
1487 bool complete = request->isComplete(); local
1492 if ((complete && !(request->isBarrier() && !can_store)) ||
|