Searched refs:cacheable (Results 1 - 3 of 3) sorted by relevance

/gem5/src/sim/
H A DProcess.py39 def map(self, vaddr, paddr, size, cacheable=False):
69 code('bool map(Addr vaddr, Addr paddr, int sz, bool cacheable=true);')
H A Dprocess.hh153 * @param cacheable Specifies whether accesses are cacheable.
157 bool map(Addr vaddr, Addr paddr, int size, bool cacheable = true);
H A Dprocess.cc384 Process::map(Addr vaddr, Addr paddr, int size, bool cacheable) argument
387 cacheable ? EmulationPageTable::MappingFlags(0) :

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