Searched refs:at (Results 1 - 25 of 81) sorted by relevance

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/gem5/src/gpu-compute/
H A Dschedule_stage.cc82 if (dispatchList->at(j).first) {
83 Wavefront *waveToMemPipe = dispatchList->at(j).first;
86 if ((i != j) && (dispatchList->at(i).first)) {
87 Wavefront *waveToExePipe = dispatchList->at(i).first;
108 waveStatusList[simdId]->at(waveToExePipe->wfSlotId)
111 dispatchList->at(i).first = nullptr;
112 dispatchList->at(i).second = EMPTY;
135 dispatchList->at(j).first = waveToBeDispatched;
137 dispatchList->at(j).second = FILLED;
139 waveStatusList[waveToBeDispatched->simdId]->at(
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H A Dscoreboard_check_stage.cc93 vectorAluInstAvail->at(unitId) = false;
102 // track which vector SIMD unit has at least one WV with a vector
104 vectorAluInstAvail->at(unitId) = vectorAluInstAvail->at(unitId) ||
107 // track how many vector SIMD units have at least one WV with a
117 // track how many vector SIMD units have at least one WV with a
143 waveStatusList[unitId]->at(wvId).second = BLOCKED;
144 Wavefront *curWave = waveStatusList[unitId]->at(wvId).first;
149 waveStatusList[unitId]->at(wvId).second = READY;
156 waveStatusList[unitId]->at(wvI
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H A Dexec_stage.cc70 if (computeUnit->isVecAlu(unitId) && vectorAluInstAvail->at(unitId)) {
109 // or issued no instructions at all
136 if (dispatchList->at(unitId).second == EMPTY) {
143 dispatchList->at(unitId).first->exec();
145 dispatchList->at(unitId).second = EMPTY;
146 dispatchList->at(unitId).first = (Wavefront*)nullptr;
167 .desc("number of cycles the CU issued at least one instruction")
185 .desc("Number of cycles at least one instruction of specific type "
H A Dof_scheduling_policy.hh64 Wavefront *cur_wave = sched_list->at(position);
75 // Check to make sure ready list had at least one schedulable wave
H A Dcondition_register_state.hh79 busy.at(regIdx) = value;
85 uint8_t status = busy.at(idx);
H A Dvector_register_file.cc79 uint8_t status = nxtBusy.at(idx);
82 status = status | (nxtBusy.at((idx + 1) % numRegs()));
91 uint8_t status = busy.at(idx);
94 status = status | (busy.at((idx + 1) % numRegs()));
103 nxtBusy.at(regIdx) = value;
106 nxtBusy.at((regIdx + 1) % numRegs()) = value;
113 busy.at(regIdx) = value;
116 busy.at((regIdx + 1) % numRegs()) = value;
H A Dlocal_memory_pipeline.cc78 || computeUnit->wfWait.at(m->pipeId).rdy())) {
101 w->computeUnit->wfWait.at(m->pipeId).set(m->time);
H A Dlds_state.hh78 T *p0 = (T *) (&(chunk.at(index)));
91 T *p0 = (T *) (&(chunk.at(index)));
224 // an event to allow the LDS to wake up at a specified time
308 "reference count should not be below zero or at zero to"
345 return refCounter.at(dispatchId).at(wgId);
443 // TODO need to set name dynamically at this point?
/gem5/src/mem/ruby/common/
H A DWriteMask.hh99 tmp = tmp & mMask.at(offset + i);
110 if (readMask.mMask.at(i)) {
111 tmp = tmp | mMask.at(i);
123 if (readMask.mMask.at(i)) {
124 tmp = tmp & mMask.at(i);
133 if (mMask.at(i)) {
144 if (!mMask.at(i)) {
156 mMask[i] = (mMask.at(i)) | (writeMask.mMask.at(i));
/gem5/ext/systemc/src/sysc/qt/md/
H A Dhppa.h19 * Department (IMMD4) at the University of Erlangen/Nuernberg Germany.
123 #define QUICKTHREADS_SPUT(top, at, val) \
124 (((qt_word_t *)(top))[-(at)] = (qt_word_t)(val))
/gem5/src/arch/hsail/
H A Dgpu_decoder.hh61 return inst < decodedInsts.size() ? decodedInsts.at(inst) : nullptr;
H A Doperand.hh112 bool init_from_vect(unsigned opOffset, const BrigObject *obj, int at,
135 init_from_vect(unsigned opOffset, const BrigObject *obj, int at) argument
140 return BaseRegOperand::init_from_vect(opOffset, obj, at, maxRegIdx,
240 init_from_vect(unsigned opOffset, const BrigObject *obj, int at) argument
245 return BaseRegOperand::init_from_vect(opOffset, obj, at, maxRegIdx,
304 init_from_vect(unsigned opOffset, const BrigObject *obj, int at) argument
309 return BaseRegOperand::init_from_vect(opOffset, obj, at, maxRegIdx,
356 bool init_from_vect(unsigned opOffset, const BrigObject *obj, int at);
422 ImmOperand<T>::init_from_vect(unsigned opOffset, const BrigObject *obj, int at) argument
436 (unsigned *)obj->getData(brigVecOp->elements + 4 * (at
550 init_from_vect(unsigned opOffset, const BrigObject *obj, int at) argument
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/gem5/ext/dsent/model/timing_graph/
H A DElectricalDriverMultiplier.cc66 max_cap = std::max(max_cap, downstream_nodes->at(i)->getTotalDownstreamCap());
H A DElectricalTimingNode.cc51 double res = m_upstream_nodes_->at(i)->getMaxUpstreamRes();
66 cap_sum += m_downstream_nodes_->at(i)->getTotalDownstreamCap();
H A DElectricalTimingTree.cc155 current_delay = extractCritPathDelay(d_nodes->at(i));
187 node_ = node_->getDownstreamNodes()->at(crit_path);
214 //If the node is not yet at max size, it is a potential choice for size up
234 node_ = node_->getDownstreamNodes()->at(crit_path);
/gem5/ext/dsent/
H A DDSENT.cc36 double freq = params.at("Frequency").toDouble();
40 params.at("TimingOptimization->StartNetNames").split("[,]");
81 // Currently we can only optimize timing at the top level
99 params.at("ReportTiming->StartNetNames").split("[,]");
120 const String& model_name = params.at("ModelName");
136 params.at(parameter_name));
154 params.at(property_name));
162 params.at("IsPerformTimingOptimization").toBool())
170 params.at("IsReportTiming") != "false")
258 params.at("ElectricalTechModelFilenam
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/gem5/src/cpu/o3/
H A Dlsq.hh166 * from initiateAcc to resource deallocation at commit or squash.
404 * The request is only added if the mask is empty or if there is at
475 RequestPtr request(int idx = 0) { return _requests.at(idx); }
480 return _requests.at(idx);
486 PacketPtr packet(int idx = 0) { return _packets.at(idx); }
859 { thread.at(tid).commitLoads(youngest_inst); }
865 { thread.at(tid).commitStores(youngest_inst); }
881 thread.at(tid).squash(squashed_num);
890 bool violation(ThreadID tid) { return thread.at(tid).violation(); }
896 return thread.at(ti
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/gem5/src/dev/x86/
H A Di8259.hh99 return *inputs.at(idx);
101 return *output.at(idx);
H A Di8042.hh135 return *mouseIntPin.at(idx);
137 return *keyboardIntPin.at(idx);
/gem5/src/mem/cache/replacement_policies/
H A Dtree_plru_rp.cc82 * Find out if the subtree at index corresponds to the right or left subtree
130 tree->at(tree_index) = right;
156 tree->at(tree_index) = !right;
171 // There must be at least one replacement candidate
184 if (tree->at(tree_index)) {
191 // The tree index is currently at the leaf of the victim displaced by the
/gem5/ext/pybind11/tests/
H A Dtest_stl.cpp56 m.def("load_vector", [](const std::vector<int> &v) { return v.at(0) == 1 && v.at(1) == 2; });
60 return v.at(0) == true && v.at(1) == false;
68 m.def("load_deque", [](const std::deque<int> &v) { return v.at(0) == 1 && v.at(1) == 2; });
83 return map.at("key") == "value" && map.at("key2") == "value2";
/gem5/util/tlm/src/
H A Dsim_control.cc119 if (flag.at(0) == '-') {
167 std::cerr << "Exit at tick " << curTick()
210 return slavePorts.at(name);
221 return masterPorts.at(name);
/gem5/ext/dsent/model/optical_graph/
H A DOpticalWavelength.cc68 OpticalDataPath& current = m_data_paths_->at(i);
112 const OpticalDataPath& current_path = getDataPaths()->at(i);
/gem5/ext/systemc/src/sysc/qt/
H A Dqt.h78 #define QUICKTHREADS_SPUT(top, at, val) \
79 (((qt_word_t *)(top))[(at)] = (qt_word_t)(val))
188 } /* Match `extern "C" {' at top. */
/gem5/ext/dsent/libutil/
H A DConfig.cc47 // Read an entire line at a time
79 // Stop at blank line, next line with a key, end of stream,
84 if(line.at(line.size() - 1) == '\\')

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