Searched refs:VECREG_UREG0 (Results 1 - 2 of 2) sorted by relevance

/gem5/src/arch/arm/
H A Dregisters.hh95 const int VECREG_UREG0 = 32; member in namespace:ArmISA
/gem5/src/arch/arm/insts/
H A Dsve_macromem.hh387 isLoad ? (IntRegIndex) VECREG_UREG0 : _base, _imm, i,
491 isLoad ? (IntRegIndex) VECREG_UREG0 : _offset, _offsetIs32,

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