Searched refs:RL (Results 1 - 5 of 5) sorted by relevance

/gem5/ext/drampower/src/
H A DMemTimingSpec.cc58 RL(0),
95 RL = getParamValWithDefault("RL", 0);
H A DMemTimingSpec.h63 int64_t RL; member in class:Data::MemTimingSpec
H A DCAHelpers.cc59 offset = memTimingSpec.RL +
H A DCmdScheduler.cc600 tSwitch_init = memTimingSpec.RL + memArchSpec.burstLength /
/gem5/src/mem/
H A Ddrampower.cc82 timingSpec.RL = divCeil(p->tCL, p->tCK);
88 timingSpec.WL = timingSpec.RL - 1;

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