Searched refs:PrefetchTLBMiss (Results 1 - 2 of 2) sorted by relevance
| /gem5/src/arch/arm/ | ||
| H A D | faults.hh | 116 PrefetchTLBMiss = AddressSizeLL + 4, enumerator in enum:ArmISA::ArmFault::FaultSource |
| H A D | tlb.cc | 1480 vaddr_tainted, ArmFault::PrefetchTLBMiss, isStage2); |
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