Searched refs:PWR_IDLE (Results 1 - 2 of 2) sorted by relevance

/gem5/src/mem/
H A Ddram_ctrl.cc721 if (dram_pkt->rankRef.pwrState == PWR_IDLE) {
1428 // not done draining until in PWR_IDLE state
1724 pwrStateTrans(PWR_IDLE), pwrStatePostRefresh(PWR_IDLE),
1725 pwrStateTick(0), refreshDueAt(0), pwrState(PWR_IDLE),
1779 pwrStatePostRefresh = PWR_IDLE;
1871 schedulePowerEvent(PWR_IDLE, curTick());
1974 } else if ((pwrState == PWR_IDLE) && (outstandingEvents == 1)) {
2047 schedulePowerEvent(PWR_IDLE, curTick());
2051 if (pwrStatePostRefresh != PWR_IDLE) {
[all...]
H A Ddram_ctrl.hh202 * PWR_IDLE : The idle state in which all banks are closed
208 * From here can transition to: PWR_IDLE, PWR_PRE_PDN,
213 * From here can transition to: PWR_IDLE
216 * From here can transition to: PWR_REF, PWR_IDLE
219 * From here can transition to: PWR_IDLE, PWR_ACT_PDN
225 PWR_IDLE = 0, enumerator in enum:DRAMCtrl::PowerState
480 bool inPwrIdleState() const { return pwrState == PWR_IDLE; }

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