| /gem5/ext/mcpat/cacti/ |
| H A D | const.h | 113 #define PCH 0 macro
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| H A D | wire.cc | 232 drain_C_(min_w_pmos, PCH, 1, 1, g_tp.cell_h_def) +
234 tr_R_on(min_w_pmos, PCH, 1);
239 drain_C_(min_w_pmos, PCH, 1, 1, g_tp.cell_h_def) +
258 drain_C_(min_w_pmos, PCH, 1, 1, g_tp.cell_h_def) +
264 drain_C_(min_w_pmos, PCH, 1, 1, g_tp.cell_h_def) +
266 tr_R_on(min_w_pmos, PCH, 1);
450 double cap_eq = 2 * drain_C_(min_w_pmos, PCH, 1, 1, g_tp.cell_h_def) +
468 res_eq = tr_R_on(inv_size * min_w_pmos, PCH, 1);
469 cap_eq = drain_C_(inv_size * min_w_pmos, PCH, 1, 1, g_tp.cell_h_def) +
548 return drain_C_(g_tp.w_iso, PCH,
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| H A D | htree2.cc | 121 (2 * drain_C_(pton_size * nsize * min_w_pmos, PCH, 1, 1, g_tp.cell_h_def)
127 (2 * drain_C_(pton_size * nsize * min_w_pmos, PCH, 1, 1, g_tp.cell_h_def)
157 double res_nor = 2 * tr_R_on(size * min_w_pmos, PCH, 1);
161 drain_C_(size * min_w_pmos, PCH, 1, 1, g_tp.cell_h_def) * 2 +
164 (drain_C_(tr_size * min_w_pmos, PCH, 1, 1, g_tp.cell_h_def) +
177 (2 * drain_C_(size * min_w_pmos, PCH, 1, 1, g_tp.cell_h_def) +
183 (2 * drain_C_(size * min_w_pmos, PCH, 1, 1, g_tp.cell_h_def) +
190 (drain_C_(size * min_w_pmos, PCH, 1, 1, g_tp.cell_h_def)
196 (drain_C_(size * min_w_pmos, PCH, 1, 1, g_tp.cell_h_def)
203 (drain_C_(size * min_w_pmos, PCH,
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| H A D | crossbar.cc | 70 // drain_C_(TriS1*min_w_pmos, PCH, 1, 1, g_tp.cell_h_def)*2 +
73 // drain_C_(TriS1*min_w_pmos, PCH, 1, 1, g_tp.cell_h_def) +
76 drain_C_(TriS1 * min_w_pmos, PCH, 1, 1, g_tp.cell_h_def) * 2 +
79 drain_C_(TriS1 * min_w_pmos, PCH, 1, 1, g_tp.cell_h_def) +
83 drain_C_(TriS2 * min_w_pmos, PCH, 1, 1, g_tp.cell_h_def);
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| H A D | decoder.cc | 197 c_intrinsic = drain_C_(w_dec_p[0], PCH, 1, 1, area.h, is_dram, false, is_wl_tr) * num_in_signals +
208 c_intrinsic = drain_C_(w_dec_p[i], PCH, 1, 1, area.h, is_dram, false, is_wl_tr) +
221 c_intrinsic = drain_C_(w_dec_p[i], PCH, 1, 1, area.h, is_dram, false, is_wl_tr) +
677 c_intrinsic = 2 * drain_C_(w_L1_nand2_p[0], PCH, 1, 1, g_tp.cell_h_def, is_dram_) +
689 c_intrinsic = drain_C_(w_L1_nand2_p[i], PCH, 1, 1, g_tp.cell_h_def, is_dram_) +
705 c_intrinsic = drain_C_(w_L1_nand2_p[i], PCH, 1, 1, g_tp.cell_h_def, is_dram_) +
714 c_intrinsic = drain_C_(w_L1_nand2_p[i], PCH, 1, 1, g_tp.cell_h_def, is_dram_) +
729 c_intrinsic = 3 * drain_C_(w_L1_nand3_p[0], PCH, 1, 1, g_tp.cell_h_def, is_dram_) +
741 c_intrinsic = drain_C_(w_L1_nand3_p[i], PCH, 1, 1, g_tp.cell_h_def, is_dram_) +
757 c_intrinsic = drain_C_(w_L1_nand3_p[i], PCH,
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| H A D | mat.cc | 489 C_intrinsic = drain_C_(ml_to_ram_wl_drv->width_n[k], PCH, 1, 1, 4 *
498 R_bl_precharge = tr_R_on(g_tp.w_pmos_bl_precharge, PCH, 1, is_dram, false, false);
541 double C_intrinsic = drain_C_(row_dec->w_dec_p[k], PCH, 1, 1, 4 *
549 double R_bl_precharge = tr_R_on(g_tp.w_pmos_bl_precharge, PCH, 1, is_dram, false, false);
789 double R_bl_precharge = tr_R_on(g_tp.w_pmos_bl_precharge, PCH, 1, is_dram, false, false);//Assuming CAM and SRAM have same Pre_eq_dr
823 + drain_C_(Wfaprechp, PCH, 1, 1, g_tp.cell_h_def, is_dram) /
830 double R_ml_precharge = tr_R_on(Wfaprechp, PCH, 1, is_dram);
852 drain_C_(Waddrnandp, PCH, 1, 1, g_tp.cell_h_def, is_dram) * 2;
918 rd = tr_R_on(W_hit_miss_p, PCH, 1, is_dram, false, false);
934 rd = tr_R_on(W_hit_miss_n, PCH,
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| H A D | technology.cc | 2657 drain_C_(g_tp.min_w_nmos_ * p_to_n_sizing_r, PCH, 1, 1, g_tp.cell_h_def) +
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| /gem5/ext/mcpat/ |
| H A D | logic.cc | 87 drain_C_(WSelORprequ, PCH, 1, 1, g_tp.cell_h_def);
93 drain_C_(WSelPp, PCH, 1, 1, g_tp.cell_h_def) +
95 drain_C_(WSelPp, PCH, 2, 1, g_tp.cell_h_def) +
97 drain_C_(WSelPp, PCH, 3, 1, g_tp.cell_h_def) +
99 drain_C_(WSelPp, PCH, 4, 1, g_tp.cell_h_def) +//precompute priority logic
102 2 * 4 * drain_C_(WSelEnp, PCH, 1, 1, g_tp.cell_h_def) +//enable logic
217 drain_C_(Wevalinvp, PCH, 1, 1, g_tp.cell_h_def) +
277 Ctotal += drain_C_(WdecNANDn, NCH, 2, 1, g_tp.cell_h_def, is_dram) + fan_in * drain_C_(WdecNANDp, PCH, 1, 1, g_tp.cell_h_def, is_dram);
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