Searched refs:MISCREG_TR_BASE (Results 1 - 4 of 4) sorted by relevance

/gem5/src/arch/x86/
H A Dfaults.cc273 tc->setMiscReg(MISCREG_TR_BASE, 0);
H A Disa.cc290 case MISCREG_TR_BASE:
H A Dprocess.cc377 tc->setMiscReg(MISCREG_TR_BASE, tss_base_addr);
/gem5/src/arch/x86/regs/
H A Dmisc.hh325 MISCREG_TR_BASE, enumerator in enum:X86ISA::MiscRegIndex

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