Searched refs:MISCREG_TLBI_ASIDE1IS_Xt (Results 1 - 5 of 5) sorted by relevance

/gem5/src/arch/arm/insts/
H A Dmisc64.cc192 case MISCREG_TLBI_ASIDE1IS_Xt:
/gem5/src/arch/arm/
H A Dmiscregs.hh554 MISCREG_TLBI_ASIDE1IS_Xt, enumerator in enum:ArmISA::MiscRegIndex
H A Disa.cc1544 case MISCREG_TLBI_ASIDE1IS_Xt:
H A Dmiscregs.cc1336 return MISCREG_TLBI_ASIDE1IS_Xt;
4219 InitReg(MISCREG_TLBI_ASIDE1IS_Xt)
/gem5/src/arch/arm/tracers/
H A Dtarmac_parser.cc515 { "tlbi_aside1is_xt", MISCREG_TLBI_ASIDE1IS_Xt },

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