Searched refs:MISCREG_TC_RESTART (Results 1 - 3 of 3) sorted by relevance

/gem5/src/arch/mips/
H A Dmt.hh144 tc->setMiscReg(MISCREG_TC_RESTART, pc.npc());
158 Addr restartPC = tc->readMiscRegNoEffect(MISCREG_TC_RESTART);
195 setRegOtherThread(tc, RegId(MiscRegClass, MISCREG_TC_RESTART),
H A Dregisters.hh150 MISCREG_TC_RESTART, enumerator in enum:MipsISA::MiscRegIndex
H A Disa.cc130 MISCREG_TC_RESTART, MISCREG_TC_HALT,

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