Searched refs:MISCREG_STATUS (Results 1 - 12 of 12) sorted by relevance

/gem5/src/arch/mips/
H A Dfaults.cc106 StatusReg status = tc->readMiscReg(MISCREG_STATUS);
117 tc->setMiscRegNoEffect(MISCREG_STATUS, status);
158 StatusReg status = tc->readMiscRegNoEffect(MISCREG_STATUS);
160 tc->setMiscReg(MISCREG_STATUS, status);
H A Dremote_gdb.cc177 r.sr = context->readMiscRegNoEffect(MISCREG_STATUS);
194 context->setMiscRegNoEffect(MISCREG_STATUS, r.sr);
H A Dinterrupts.cc116 StatusReg status = tc->readMiscRegNoEffect(MISCREG_STATUS);
137 StatusReg M5_VAR_USED status = tc->readMiscRegNoEffect(MISCREG_STATUS);
H A Dutility.hh77 RegVal Stat = tc->readMiscReg(MISCREG_STATUS);
H A Dmt.hh199 StatusReg status = tc->readMiscReg(MISCREG_STATUS);
310 StatusReg status = tc->readMiscRegNoEffect(MISCREG_STATUS);
316 tc->setMiscRegNoEffect(MISCREG_STATUS, status);
328 StatusReg status = tc->readMiscRegNoEffect(MISCREG_STATUS);
H A Dregisters.hh181 MISCREG_STATUS = 96, //Bank 12: 96-103 enumerator in enum:MipsISA::MiscRegIndex
H A Dfaults.hh92 StatusReg status = tc->readMiscReg(MISCREG_STATUS);
283 StatusReg status = tc->readMiscReg(MISCREG_STATUS);
H A Disa.cc128 uint32_t per_tc_regs[] = { MISCREG_STATUS,
327 StatusReg status = readMiscRegNoEffect(MISCREG_STATUS);
339 setMiscRegNoEffect(MISCREG_STATUS, status);
343 setRegMask(MISCREG_STATUS, stat_Mask);
/gem5/src/arch/riscv/
H A Dfaults.cc61 STATUS status = tc->readMiscReg(MISCREG_STATUS);
127 tc->setMiscReg(MISCREG_STATUS, status);
144 STATUS status = tc->readMiscReg(MISCREG_STATUS);
147 tc->setMiscReg(MISCREG_STATUS, status);
H A Dinterrupts.hh78 STATUS status = tc->readMiscReg(MISCREG_STATUS);
H A Disa.cc69 miscRegFile[MISCREG_STATUS] = (2ULL << UXL_OFFSET) | (2ULL << SXL_OFFSET) |
H A Dregisters.hh143 MISCREG_STATUS, enumerator in enum:RiscvISA::MiscRegIndex
439 {CSR_USTATUS, {"ustatus", MISCREG_STATUS}},
483 {CSR_SSTATUS, {"sstatus", MISCREG_STATUS}},
500 {CSR_MSTATUS, {"mstatus", MISCREG_STATUS}},

Completed in 23 milliseconds