Searched refs:MISCREG_SF_MASK (Results 1 - 5 of 5) sorted by relevance

/gem5/src/arch/x86/regs/
H A Dmsr.cc118 MsrVal(0xC0000084, MISCREG_SF_MASK),
H A Dmisc.hh253 MISCREG_SF_MASK, enumerator in enum:X86ISA::MiscRegIndex
/gem5/src/arch/x86/
H A Dutility.cc150 tc->setMiscReg(MISCREG_SF_MASK, 0);
H A Dprocess.cc458 tc->setMiscReg(MISCREG_SF_MASK, sfmask);
/gem5/src/gpu-compute/
H A Dgpu_tlb.cc529 regNum = MISCREG_SF_MASK;

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