Searched refs:MISCREG_SEDELEG (Results 1 - 2 of 2) sorted by relevance
| /gem5/src/arch/riscv/ | ||
| H A D | faults.cc | 79 bits(tc->readMiscReg(MISCREG_SEDELEG), _code) != 0) { |
| H A D | registers.hh | 244 MISCREG_SEDELEG, enumerator in enum:RiscvISA::MiscRegIndex 484 {CSR_SEDELEG, {"sedeleg", MISCREG_SEDELEG}}, |
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