Searched refs:MISCREG_SCOUNTEREN (Results 1 - 2 of 2) sorted by relevance

/gem5/src/arch/riscv/
H A Disa.cc72 miscRegFile[MISCREG_SCOUNTEREN] = 0x7;
89 counteren = MISCREG_SCOUNTEREN;
H A Dregisters.hh247 MISCREG_SCOUNTEREN, enumerator in enum:RiscvISA::MiscRegIndex
488 {CSR_SCOUNTEREN, {"scounteren", MISCREG_SCOUNTEREN}},

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