Searched refs:MISCREG_PRID (Results 1 - 2 of 2) sorted by relevance

/gem5/src/arch/mips/
H A Dregisters.hh190 MISCREG_PRID = 120, //Bank 15: 120-127, enumerator in enum:MipsISA::MiscRegIndex
H A Disa.cc180 PRIdReg procId = readMiscRegNoEffect(MISCREG_PRID);
185 setMiscRegNoEffect(MISCREG_PRID, procId);
190 setRegMask(MISCREG_PRID, procIDMask);

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