Searched refs:MISCREG_PERF_EVT_SEL0 (Results 1 - 3 of 3) sorted by relevance

/gem5/src/arch/x86/regs/
H A Dmsr.cc123 MsrVal(0xC0010000, MISCREG_PERF_EVT_SEL0),
H A Dmisc.hh260 MISCREG_PERF_EVT_SEL0 = MISCREG_PERF_EVT_SEL_BASE, enumerator in enum:X86ISA::MiscRegIndex
/gem5/src/gpu-compute/
H A Dgpu_tlb.cc544 regNum = MISCREG_PERF_EVT_SEL0;

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