Searched refs:MISCREG_MTRR_PHYS_MASK_5 (Results 1 - 3 of 3) sorted by relevance
| /gem5/src/arch/x86/regs/ | ||
| H A D | msr.cc | 64 MsrVal(0x20B, MISCREG_MTRR_PHYS_MASK_5), |
| H A D | misc.hh | 181 MISCREG_MTRR_PHYS_MASK_5, enumerator in enum:X86ISA::MiscRegIndex |
| /gem5/src/gpu-compute/ | ||
| H A D | gpu_tlb.cc | 367 regNum = MISCREG_MTRR_PHYS_MASK_5; |
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