Searched refs:MISCREG_MCOUNTEREN (Results 1 - 2 of 2) sorted by relevance

/gem5/src/arch/riscv/
H A Disa.cc71 miscRegFile[MISCREG_MCOUNTEREN] = 0x7;
86 counteren = MISCREG_MCOUNTEREN;
H A Dregisters.hh218 MISCREG_MCOUNTEREN, enumerator in enum:RiscvISA::MiscRegIndex
506 {CSR_MCOUNTEREN, {"mcounteren", MISCREG_MCOUNTEREN}},

Completed in 5 milliseconds