Searched refs:MISCREG_MCAUSE (Results 1 - 2 of 2) sorted by relevance
| /gem5/src/arch/riscv/ | ||
| H A D | faults.cc | 107 cause = MISCREG_MCAUSE; 148 tc->setMiscReg(MISCREG_MCAUSE, 0); |
| H A D | registers.hh | 221 MISCREG_MCAUSE, enumerator in enum:RiscvISA::MiscRegIndex 509 {CSR_MCAUSE, {"mcause", MISCREG_MCAUSE}}, |
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