Searched refs:MISCREG_MC1_STATUS (Results 1 - 3 of 3) sorted by relevance

/gem5/src/arch/x86/regs/
H A Dmsr.cc91 MsrVal(0x405, MISCREG_MC1_STATUS),
H A Dmisc.hh215 MISCREG_MC1_STATUS, enumerator in enum:X86ISA::MiscRegIndex
/gem5/src/gpu-compute/
H A Dgpu_tlb.cc448 regNum = MISCREG_MC1_STATUS;

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