Searched refs:MISCREG_ISA (Results 1 - 2 of 2) sorted by relevance
| /gem5/src/arch/riscv/ | ||
| H A D | isa.cc | 65 miscRegFile[MISCREG_ISA] = (2ULL << MXL_OFFSET) | 0x14112D; |
| H A D | registers.hh | 138 MISCREG_ISA, enumerator in enum:RiscvISA::MiscRegIndex 501 {CSR_MISA, {"misa", MISCREG_ISA}}, |
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