Searched refs:MISCREG_IP (Results 1 - 2 of 2) sorted by relevance
| /gem5/src/arch/riscv/ |
| H A D | isa.cc | 144 case MISCREG_IP:
187 case MISCREG_IP:
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| H A D | registers.hh | 144 MISCREG_IP, enumerator in enum:RiscvISA::MiscRegIndex
446 {CSR_UIP, {"uip", MISCREG_IP}},
493 {CSR_SIP, {"sip", MISCREG_IP}},
511 {CSR_MIP, {"mip", MISCREG_IP}},
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