Searched refs:MISCREG_IORR_MASK0 (Results 1 - 4 of 4) sorted by relevance

/gem5/src/arch/x86/regs/
H A Dmsr.cc134 MsrVal(0xC0010018, MISCREG_IORR_MASK0),
H A Dmisc.hh281 MISCREG_IORR_MASK0 = MISCREG_IORR_MASK_BASE, enumerator in enum:X86ISA::MiscRegIndex
/gem5/src/arch/x86/
H A Dutility.cc165 tc->setMiscReg(MISCREG_IORR_MASK0, 0);
/gem5/src/gpu-compute/
H A Dgpu_tlb.cc577 regNum = MISCREG_IORR_MASK0;

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