Searched refs:MISCREG_INSTRET (Results 1 - 2 of 2) sorted by relevance

/gem5/src/arch/riscv/
H A Disa.cc135 case MISCREG_INSTRET:
136 if (hpmCounterEnabled(MISCREG_INSTRET)) {
H A Dregisters.hh148 MISCREG_INSTRET, enumerator in enum:RiscvISA::MiscRegIndex
452 {CSR_INSTRET, {"instret", MISCREG_INSTRET}},
533 {CSR_MINSTRET, {"minstret", MISCREG_INSTRET}},

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