Searched refs:MISCREG_INDEX (Results 1 - 2 of 2) sorted by relevance
| /gem5/src/arch/mips/ | ||
| H A D | registers.hh | 133 MISCREG_INDEX = 0, //Bank 0: 0 - 3 enumerator in enum:MipsISA::MiscRegIndex |
| H A D | isa.cc | 387 setRegMask(MISCREG_INDEX, mask); |
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