Searched refs:MISCREG_IGNNE (Results 1 - 4 of 4) sorted by relevance

/gem5/src/arch/x86/regs/
H A Dmsr.cc139 MsrVal(0xC0010115, MISCREG_IGNNE),
H A Dmisc.hh289 MISCREG_IGNNE, enumerator in enum:X86ISA::MiscRegIndex
/gem5/src/arch/x86/
H A Dutility.cc196 tc->setMiscReg(MISCREG_IGNNE, 0);
/gem5/src/gpu-compute/
H A Dgpu_tlb.cc592 regNum = MISCREG_IGNNE;

Completed in 9 milliseconds