Searched refs:MISCREG_ICV_CTLR_EL1 (Results 1 - 2 of 2) sorted by relevance

/gem5/src/dev/arm/
H A Dgic_v3_cpu_interface.cc560 return readMiscReg(MISCREG_ICV_CTLR_EL1);
584 case MISCREG_ICV_CTLR_EL1: {
1131 return setMiscReg(MISCREG_ICV_CTLR_EL1, val);
1207 case MISCREG_ICV_CTLR_EL1: {
1210 isa->readMiscRegNoEffect(MISCREG_ICV_CTLR_EL1);
/gem5/src/arch/arm/
H A Dmiscregs.hh789 MISCREG_ICV_CTLR_EL1, enumerator in enum:ArmISA::MiscRegIndex

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