Searched refs:MISCREG_ICV_BPR0_EL1 (Results 1 - 2 of 2) sorted by relevance

/gem5/src/dev/arm/
H A Dgic_v3_cpu_interface.cc316 return readMiscReg(MISCREG_ICV_BPR0_EL1);
331 case MISCREG_ICV_BPR0_EL1: {
1050 return setMiscReg(MISCREG_ICV_BPR0_EL1, val);
1093 case MISCREG_ICV_BPR0_EL1:
1097 misc_reg == MISCREG_ICV_BPR0_EL1 ? Gicv3::G0S : Gicv3::G1NS;
/gem5/src/arch/arm/
H A Dmiscregs.hh761 MISCREG_ICV_BPR0_EL1, enumerator in enum:ArmISA::MiscRegIndex

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